1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
In recent years, an integration of a circuit chip including LSI (Large System Integration) is rapidly developing. Along with this, an I/O (Input/Output) circuit itself composed of a power transistor or the like that is mounted to a circuit chip is strongly demanded to reduce its size.
In U.S. Pat. No. 5,581,109, a technique for reducing the size of an I/O circuit having a plurality of pads and transistor array areas or the like is disclosed.
FIG. 16 shows a conventional I/O circuit 100. As shown in FIG. 16, the I/O circuit 100 includes connection lines 101, first AREA102, second AREA103, source electrode pads 104 and drain electrode pads 105.
The I/O circuit 100 is a transistor divided into the first AREA102 and second AREA103. In each of the first AREA102 and second AREA103, drain regions (not shown) and source regions (not shown) are formed with gate lines (not shown) provided. The drain regions formed in the first AREA102 are connected with the drain regions formed in the second AREA103. The source regions formed in the first AREA102 are connected with the source regions formed in the second AREA103. Furthermore, the gate lines formed in the first AREA102 are connected with the gate lines formed in the second AREA103 via the connection lines 101.
Conventionally, the connection line 101 has been provided in a wiring layer located in an upper layer of a gate wiring layer. That is, after placing the gate line and depositing an insulating layer over the gate line, the connection line 101 has been provided over the insulating layer.
However, it has now discovered that placing the connection lines 101 as described above makes it harder to reduce the size of the circuit chip. More specifically, a line provided in the same layer with the connection line 101 can not be used for connecting a node N1 and a node N2 as shown in FIG. 16. Therefore, a line provided in a different layer from the layer including the connection line 101 is used to connect the nodes N1 and N2 when the area below the pads 104 and 105 is required to be used, and thereby causing to increase the number of wiring layers of the I/O circuit 100.
Furthermore, to connect the nodes N1 and N2 by the line provided in the same layer with the layer having the connection line 101, the line must be provided bypassing the I/O circuit 100.